ISBN: 9783659534157

[ED: Taschenbuch], [PU: LAP Lambert Academic Publishing], Neuware - In spite of the huge research efforts and respectable scientific achievements, there are still challenges regarding the… Plus…

[ED: Taschenbuch], [PU: LAP Lambert Academic Publishing], Neuware - In spite of the huge research efforts and respectable scientific achievements, there are still challenges regarding the use of commercial ASIC technologies in space and safety-critical applications. The most important challenges are: 1. Radiation-hardened technologies are expensive (qualification and quality requirements are severe) and commercially not attractive (small volume production). 2. There is no standard integrated framework of circuit design techniques that provides simultaneous SEU, SET, and SEL fault-tolerance. 3. There is no standard design automation flow for fault-tolerant digital ASICs and SOCs. This book presents a design methodology for fault-tolerant ASIC that is based on redundant circuits with latchup protection and additional implementation steps during logic synthesis and layout generation. The proposed design approach provides the ASICs immune to the upsets, transients, and latchup faults by combining and integrating different fault-tolerant techniques in a carefully designed procedure., DE, [SC: 0.00], Neuware, gewerbliches Angebot, 220x150x15 mm, 252, [GW: 392g], PayPal, Offene Rechnung, Banküberweisung, Sofortüberweisung, Internationaler Versand<

ISBN: 9783659534157

Paperback, [PU: LAP LAMBERT Academic Publishing], In spite of the huge research efforts and respectable scientific achievements, there are still challenges regarding the use of commercial… Plus…

Paperback, [PU: LAP LAMBERT Academic Publishing], In spite of the huge research efforts and respectable scientific achievements, there are still challenges regarding the use of commercial ASIC technologies in space and safety-critical applications. The most important challenges are: 1. Radiation-hardened technologies are expensive (qualification and quality requirements are severe) and commercially not attractive (small volume production). 2. There is no standard integrated framework of circuit design techniques that provides simultaneous SEU, SET, and SEL fault-tolerance. 3. There is no standard design automation flow for fault-tolerant digital ASICs and SOCs. This book presents a design methodology for fault-tolerant ASIC that is based on redundant circuits with latchup protection and additional implementation steps during logic synthesis and layout generation. The proposed design approach provides the ASICs immune to the upsets, transients, and latchup faults by combining and integrating different fault-tolerant techniques in a carefully designed procedure., Electronics Engineering<

ISBN: 9783659534157

Edition reliée

*Design Methodology for highly Reliable Digital ASIC Designs* - Applied to Network-Centric System Middleware Switch Processor / Taschenbuch für 69.99 € / Aus dem Bereich: Bücher, Taschenb… Plus…

*Design Methodology for highly Reliable Digital ASIC Designs* - Applied to Network-Centric System Middleware Switch Processor / Taschenbuch für 69.99 € / Aus dem Bereich: Bücher, Taschenbücher, Naturwissenschaft Medien > Bücher nein Taschenbuch Hardcover;Naturwissenschaften, Medizin, Informatik, Technik;Elektronik, Elektrotechnik, Nachrichtentechnik, LAP LAMBERT Academic Publishing<

ISBN: 3659534153

Design Methodology for highly Reliable Digital ASIC Designs ab 69.99 € als Taschenbuch: Applied to Network-Centric System Middleware Switch Processor. Aus dem Bereich: Bücher, Wissenschaf… Plus…

Design Methodology for highly Reliable Digital ASIC Designs ab 69.99 € als Taschenbuch: Applied to Network-Centric System Middleware Switch Processor. Aus dem Bereich: Bücher, Wissenschaft, Technik, Medien > Bücher, LAP LAMBERT Academic Publishing<

2014, ISBN: 3659534153

Kartoniert / Broschiert, mit Schutzumschlag 11, [PU:LAP LAMBERT Academic Publishing]